As is known, video graphics circuits are utilized in computers to process images for subsequent display on a display device, which may be a computer monitor, a television, an LCD panel, and/or any other device that displays pixel information. Typically, the central processing unit of a computer generates geometric data regarding the images to be rendered and provides the geometric data to the video graphic circuit. The video graphic circuit, upon receiving the geometric data, processes it to generate pixel data of the image. As the video graphics circuit is generating the pixel data, it stores the pixel data in a frame buffer. When the video graphic circuit has processed a full frame of geometric data, the frame buffer is full and provides the pixel data to the display device.
Typically, the video graphics circuit includes a culling module, a set-up module, and a raster module. The central processing unit includes software to generate geometric information for the images to be rendered. The geometric information is provided to the culling module, which, in turn, produces culling information. As is known, the culling information indicates which triangles of objects of the image are front facing and which are back facing. The front facing triangles are those that are visible to a viewer on the display device and the back facing of those that are not viewable. In addition, the culling module passes the geometric information of the front facing triangles, or objects, to the set-up module. The set-up module in-turn generates set-up information based on the culling information 32 and the geometric, or geometry, information. The set-up information includes physical coordinates, texture coordinates, color information, etc. for a given pixels within the object. The raster module receives the set-up information and generates the pixel data based on set-up information. The pixel data is subsequently provided to the display device for display.
The culling module, the set-up module, and the raster module of the video graphics circuit are serially coupled therefor their processes are interdependent. As such, bottlenecks may occur depending on the type of information being processed. For example, if a plurality of very small triangles is being processed, a bottleneck will occur at the set-up module, since it is generating the object parameters for a plurality of objects. Alternatively, a bottleneck may arise at the raster module when large triangles are being rendered. As such, there are several instances during the rendering of most frames where one or more modules are stalled waiting for the other module to complete its particular function.
Typically, first-in first-out (FIFO) buffers will be located between the modules of the video graphics circuit to provide buffering. However, the FIFOs are relatively small and often encounter an overflow or underflow condition, which stalls the associated intra-video graphics modules. To reduce the overflow/underflow condition, one could increase the size of the FIFOs. While this is theoretically possible, it is impractical due to the additional memory needed and its corresponding cost.
Therefore, a need exists for a method and apparatus that increases intra-video graphic processing concurrency.